1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
A semiconductor device to be herein discussed is found, for example, in Japanese Laid-open patent publication No. H05-190783. The semiconductor device disclosed in this document is shown in FIG. 11. This semiconductor device includes a deep well provided on the side of a digital circuit, to thereby adjust impurity concentration distribution.
As shown in FIG. 11, a p-substrate 1 includes selectively formed n-wells 2, 3, 6 and a deep n-well 4. The n-wells 3 and 6 are located so as to partially overlap the deep n-well 4. Also, the p-substrate 1 includes a p-well 5′ and the deep n-well 4 includes a p-well 5.
Here, it is assumed that the digital circuit is constituted of a p-channel transistor formed in the n-well 3 and an n-channel transistor formed in the p-well 5. Likewise, it is assumed that an analog circuit is constituted of a p-channel transistor formed in the n-well 2 and an n-channel transistor formed in the p-well 5′. The potential of the n-well 3 including the p-channel transistor for the digital circuit is supplied by a digital positive power source DVDD, while the potential of the p-well 5 including the n-channel transistor for the digital circuit is supplied by a digital negative power source DVSS. The potential of the n-well 2 including the p-channel transistor for the analog circuit is supplied by an analog positive power source AVDD, while the potential of the p-well 5′ including the n-channel transistor for the analog circuit is supplied by an analog negative power source AVSS.
Another semiconductor device to be herein discussed is found, for example, in Japanese Laid-open patent publication No. H06-69436. FIG. 12 shows the semiconductor device disclosed therein. This semiconductor device is of a similar structure to that disclosed in Japanese Laid-open patent publication No. H05-190783, except that a deep well is provided on the side of an analog circuit.
In the semiconductor devices according to the foregoing documents, however, when the plan-view area of the deep n-well 4 becomes larger, it becomes difficult to reduce a noise that intrudes into the analog circuit from the digital circuit. To be more detailed, impedance is usually defined by a formula:Z=R+j(ωL−1/ωC).
Accordingly, an increase in the capacitance C (increase in the p-substrate 1-deep n-well 4 junction capacitance) leads to a decrease in the impedance Z. This inhibits reducing the noise that intrudes into the analog circuit from the digital circuit.